Design of powerplane decoupling manually with SIwave

How to use SIwave to do manual power integrity? There are many ways to achieve power integrity. We are going to present here one technique.

The designer needs to remember two things when doing power integrity:

• First, do not try to design all the powerplanes simultaneously. Do them one by one.
• Second, do not use ideal capacitors. Use the models of the manufacturers. These models have non-zero ESL and ESR. Ideal capacitors have zero ESL and ESR, and that is not right.

Step one: find the equivalent circuit of the VRM, or some call it the output impedance of the VRM. Users will find them in the VRM datasheet. It is usually an Inductance plus a resistor. The specification says that the values are Inductance =1nH and the resistance is 10mOhm.

Step two: Verify if the VRM impedance meets the impedance specifications. Go to Tools> Capacitors/Inductors Library Browser. This is a very powerful tool in SIwave, but not so many know about it or use it.

Figure.1

Add the VRM impedance; the graph in black represents the VRM impedance alone. Also, the impedance specifications of the 1.2V power plane should be added. The specifications are 30mOhm up to 100MHz.

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The VRM by itself is badly violating the specification. In this case, decoupling caps must be added right at the output of VRM output. But which one to choose? Refer to the table below. That shows the active band of many famous standard caps. Choose the ones that are inside the band of interest. In this case, it is the 10nF, active around the 70MHz.

Figure.4

We filter the manufacturer, and we select Murata. Users can choose any other supplier, and we select 0402 and the 10nF option. From the list, select one option. Immediately, the tool adds one decoupling cap.

Now, there are three curves: the original VRM impedance curve, the cap curve, and the new curve. The cap curve is half inside the band; it is OK but not recommended. It is better to choose something that is completely inside the band. Choose the next 100nF. Disable the 10nF one, then change the filter and select a cap. Good. Need to add more to it to push the curve down, and the number is 7. That is good enough. Remember, the purpose is to lower the curve and not to meet the specifications. Move on to the next cap, 1uF, change the filter, add 3. Finally, need to add 10uF caps.

Figure.5

Add these in an Excel. Need to add these to the PCB. But sometimes the number of caps is large. It is better to add these in parallel. Add the 100nF ones alone, the 1uF alone. Back to the model and add these three capacitors right at the output of the VRM. It is ideal but good enough.

If there are any recommended decoupling caps by the supplier, and usually there are, start by adding them to this tool, then add more as required.

Step three: Add the capacitors to the model. Also, add the inductor that represents the VRM equivalent circuit. Go to PI solver.

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It is important to start from here because the interface will help the user identify the components on the 1.2Volt. Select the CPU and the load. Always simulate one power plane at a time and one load at a time. Make sure that the model has one port. Finish the setup and specify the frequency band. And run.

We have a solution: right-click here, display results, and select Z. Looking at Z11. Z11 is the same as the impedance of the model. That is why one must use single-port models. If the user uses two or more ports, then he needs to do lots of post-processing to derive the impedance. Z11 is the impedance that the CPU is looking at. It includes the VRM, the decoupling caps, plus the impedance of the power plane. This is the curve that we want to optimize.

Figure. 8

Add the limit line of the specifications. Again, The VRM+Decap+PCB does not meet the specifications. Check this point, which is the value of the impedance at 100MHz. Also, check the DC point. Record the two values.

Step four: optimize VRM+PCB. Go back to the Tools. Remove all caps. First, one will see the contribution of the VRM alone. Need to change that to match the DC and 100MHz points obtained from the previous step. Select the values ESL=0.44nH, and ESR=12.5mOhm.

Remember when we did the VRM, we said not to choose a cap that is half inside, like the 10nF. On the CPU side, it is highly recommended that users use the one at the edge of the band. Start with the 10nF, use 8, maybe 10, and be generous. Then, next to the 100nF, need 6 of them, and finally, the 1uF, 3 of them. Back to Excel, and add them again in parallel.

Figure.9

Step 5: add the new capacitors to the model at the CPU. And run the PI again. Call the solution VRM_VRMDecap_PCB_PCBDecap. The results should show a major improvement in the impedance curve.

Remember: Start by adding the recommended caps by the supplier, then add more. Add the CPU-recommended decoupling first before adding more. This is important because the supplier's decoupling caps satisfy another condition. When placing the calculated caps, start by placing the smallest ones as close to the die. Then, place the next one in the next row, and so on. The first set of caps should be big enough to supply the die with all the current it needs without causing the voltage to drop below a specific delta. If one integrates the current curve over time, that will give the charge. Delta V is equal to the required charge divided by the capacitance of all the caps of the first row. The Delta V must be below the tolerance. That is why starting with the supplier's recommended caps is important. They take care of that calculation.

Figure.10

Step 6: Go back and verify all the other loads on the 1.2Volt. Simply go back to the PI solver, and change the port to another load. Run the model with all the caps on it. Each load has its own impedance specifications. It is different from one load to another. Once a user gets a solution, regenerate the curve in Tools and add more caps. The new caps will be placed at the input of the second load. And so on.

The next steps are trivial: add these caps in the layout properly, then import the model and solve. One powerplane at a time, and one load at a time.

It is highly recommended that the PI advisor be used at the end to optimize the number of caps and their values.