HFSS-IC: Features and Advantages

Why HFSS-IC?

Ansys has released HFSS-IC, a new tool aimed at small to medium-sized businesses. It enables the design of complex die assemblies mounted on packages and integrated onto printed circuit boards. The solution includes three robust solvers—HFSS, Q3D, and RaptorX—and offers a broad set of features compared to other market alternatives:

• Can read GDS files and supporting files (*.map or *.xml).
• Can read foundry-encrypted models. Approved by the main foundry.
• 3 Solvers (HFSS/Q3D/RaptorX) for complete design capabilities at all design stages.
• HFSS is the industry standard for solving electromagnetic problems
• Most foundries approve RaptorX.
• Supports complicated die(s)-on-die-on-package configurations.
• Innovative tools to simplify the model and the meshing.
• Parametrization for the three solvers, with smart optimizer using Optislang.
• Linked to the AEDT circuit, 2-way connection.
• Affordable price for small and medium companies.

GDS files:

The GDS file format is the most commonly used format in the dies (chips) industry. The HFSS-IC solution is capable of reading GDS files as well as stackup files such as .map, .xml, and *.ircx, among others. From the main menu, File>Import>GDS files:

After selecting the GDS file, AEDT displays the list of layers, a list of nets, and ports. It also gives the user the capability to import control files:

You can upload the following control/supporting file types: *.xml, *.tech, *.layermap, *.ircx, *.itf,* .vlc.tech, and *.map files.

The example used for this blog is a silicon Interposer:

HFSS/3D Layout default mode and HFSS-IC mode.

In the HFSS/3D Layout default mode, the user has access to HFSS, planar, and SIwave DICR/PI solvers.

The user can switch to the HFSS-IC mode by right-clicking on the name of the model>Design Settings> Design mode.

Switching to the IC mode gives the user access to the three solvers: HFSS, Q3D, and RaptorX.

The following table summarizes the main features of each type:

When to use each solver? Each solver has its capabilities and strengths. The user needs to select the right tool for each stage. These tools are all that the user needs to do for fast and smooth design.

IC mode Stackup

The first thing to check is the stackup in the model. Select the stackup icon:

IC-mode stackups are always overlapping stackups. It is possible to overlap different layers in this mode. A user simply needs to specify the lower and upper dimensions of each layer. In addition to changing the layers and materials, the user can also add effects such as etching and surface roughness. There are also VIA layers in the IC mode. Via layers' lower and upper dimensions are specified using the Metal layer name, for example, M5, M6, etc.

IC mode Ports

In HFSS, users can add ports in various ways. The three solvers accept all types. The first way to add ports is to select a network and then right-click to add ports at both ends of the network.

The other way is to select a component and then right-click to add ports:

These two ways create a coaxial-gap type port.

Model Editing

It is highly recommended that RaptorX be used during the design phase, especially during optimization. To obtain more accurate results, the user must also be able to utilize HFSS. The IC mode was equipped with smart tools to make modifications to the design and eliminate small dimensions, thereby preventing the HFSS from running for an excessively long period of time.

However, before using any of them, the user needs to modify the settings. Click on the setting button:

To understand the meaning of each number in the settings, we go back to the tools:

• Snap vias: This option will change the cross-section of the vias to match the size of the pads in the upper or lower layer. The change happens if the delta is less than what is specified in the Via snapping criteria in the setting.
• Snap Primitives: This option changes the shape of the nets in the signal layers to match each other. The change happens if the delta is less than what is specified in the Primitive snapping criteria in the setting.
• Group vias: This option groups vias into a single net if they are spaced less than what is specified in the Via Grouping criteria in the settings.
• Wrap Geometry: This option groups nets or vias into a single net/single via and closes gaps if the gaps between objects are less than the number specified in the geometry wrapping criteria in the settings.
• Remove Holes: If the net in the signal layers has small holes with a cross-section less than the number specified in "Remove small metal islands", it will be filled.
• Remove Islands: This option simply deletes all small islands. The decision is based on the Remove Small Metal Islands criteria in the setting.

Difference between the three solvers: Results

The following graph shows the difference between the three solvers. Note that we have solved Q3D for up to 1 GHz. That is all that we need to extract the RLCG of the nets.

Both HFSS and RaptorX gave very close results. That indicates that the user can trust RaptorX during the optimization process. The following table shows the time it took to solve for each solver. HFSS, using the default setup, took 5 times longer than RaptorX. This time can be improved if the user performs smart meshing by controlling the mesh in all objects.

Summary

HFSS-IC is a robust and budget-friendly solution designed for small to medium-sized businesses. It integrates the full capabilities of both the HFSS and RaptorX solvers. This tool supports the design of a wide array of configurations, including dies, stacked dies, dies on packages, and even complex assemblies mounted on PCBs—without limitations. Users can extract parasitic elements, design inductors, optimize transitions and power dividers, mitigate crosstalk, and more.