PCB Simulation

The increasing complexity of nowadays wireless RF devices increases the demand for accurate and efficient simulations of large and complex PCB designs. Identifying and predicting potential issues early in the design process saves resources, time, and money. SIwave helps you model, simulate and validate high-speed channels and complete power delivery systems typical in modern high-performance electronics. It accurately extracts multi-gigabit SERDES and memory buses, providing product sign-off compliance for various designs. SIwave’s full wave extraction of complete power distribution networks (PDN) enables you to verify noise margins and ensure impedance profiles are met through automatic decoupling analysis in low-voltage designs.

Overview

In this blog we will be using the ANSYS SIwave and ANSYS Nexxim transient solvers to perform PCIe Gen4 signal integrity (SI) analysis for ensuring reliable high speed data transmission. Using the SIwizard, we will automate the signal integrity analysis to setup up the circuit transient simulation based on the SIwave extracted SYZ data. we will also show how to add equalization to improve the quality of the transmitted signal. 

NETS Definition

Before launching the SIwizard, we will define first the extended nets. Using auto identify, we can identify the extended Nets using the Net name differentiator "_CAP", as you see below.

SIwizard

To launch the SIwizard, go to the simulation menu and click on SIwizard.

In the below window, we need to select the nets to analyze. We will include one differential Rx net "Diff_PCIe_Gen4_Rx0" and  1 extended differential Tx nets as shown below.

After clicking on Next, we will need to specify the receiver and transmitter. Also define the PCIe excitation source to the driver, as seen below.

If the excitation source is not available, you can click on add a new source and input the needed data.

Then click on Next until you get to the window below. Here will define the simulation setup as seen below, and select to use ANSYS Electronics Desktop SIwave Dynamic Link option. The min rise time should be entered based on the PCIe Gen4 standards which is 18 ps.

Once you click on Ok, the AEDT project should be created and both the SIwave and Circuit transient simulation should run automatically.

SIwave SYZ Simulations

After the simulation completes, we can view the SYZ parameter data in SIwave as seen below. 

Create Eye Diagram Plot

The SIwizard automatically generates the circuit design with the complete setup for transient and quick eye analysis. The eye source is defined based on what we defined in the SI wizard. Below is the circuit design and the eye source definition.

After both the SIwave and transient simulations are done, we can create the eye diagram plot following the below procedures;

• Right Click on Results, Select Create Eye Diagram Report, then Select Rectangular Plot

• In the Report dialog box, under solution tab, set: 
  
  • Solution to QuickEyeAnalysis
    • note you can also use the Transient setup to generate the eye diagram, quick eye is faster and include more bits.
  • Domain to Time
  • Probe: AEYEPROBE(PCIe_Gen4_RX0_P_AP26_U1_diff_rx_eye) for Rx,  AEYEPROBE(PCIe_Gen4_TX0_P_B2_X1_diff_rx_eye) for Tx
  • Unit Interval: 6.25e-11s
  • Click on the New Report button 
• Click on Close to close the Report dialog box

Below is the diagram plot for both or Rx and Tx. We clearly see wide and open eye in the diagrams with minimal distortion.

we can also define the PCIe Gen4 mask to be viewed with the eye diagram report. In order to add the data mask, open Edit eye mask dialog box:

• In the eye diagram plot, click on or near the X-axis (Time) at the bottom of the plot to select the X-axis  
• In the Properties window select the Mask tab
• Click the Edit button, which brings up the Edit eye mask dialog box

• In the Edit eye mask dialog box, click on the Edit button, which opens the Edit Dataset window
• In the Edit Dataset window, in the Coordinates area, enter the mask data:
• Time[ps]: 55.625ps and Voltage[mV]: 0mV
• Time[ps]: 75ps and Voltage[mV]: -75mV
• Time[ps]: 84.375ps and Voltage[mV]: 0mV
• Time[ps]: 75ps and Voltage[mV]: 75mV
• Time[ps]: 65.625ps and Voltage[mV]: 0mV

Note: the mask points are defined based on the PCIe Gen4 standards which has an eye width of 0.3ps and eye height of 15 mv. According to the Eye diagram data, we find the center point which is 75ps and 0 mV and then we define the mask as shown in the below figure.  

And below is the eye diagram plot for Rx with the data mask shown.

Equalization

In Circuit we can also define equalization to compensate for signal distortion introduced by a transmission channel, improving the quality and reliability of data transmission. To add the equalization we need to modify both of the eye source and the eye probe.

To modify the eye source, double click on the source, and select the Equalization tab as seen below.

According to the PCIe gen 4 standards, the FFE has 3 taps (-1,0,1). The ref probe that corresponds to the source should be selected. Similarly we do the same thing to the other Tx eye source. 

For the eye probe, we need to define the DFE data which has 2 taps, as seen below.

and we also need to define the CTLE data, by selecting PCIe gen4 standard from the standards list under the generic rational function for the CTLE. The CTLE pole data are 4E9 and 16E9 according to the standards.

The video link below shows an illustration on how to do these steps in detail, and the model shown is available in the downloadable resources.

Downloadable Resources

SIwave Project