Every PCB design includes at least one power plane that should be analyzed using the PI (AC) solver. Even if the loads draw primarily DC current, there are transient phenomena that cannot be ignored — such as power-up sequencing, startup inrush current, and power-gating or sleep–wake transitions.
For DC or steady-state loads, the designer should still perform a basic PI analysis using the PI Wizard and the Resonant Mode solver in SIwave. The goal is to verify that the power plane does not exhibit resonance within the frequency band associated with any current variations. In this case, no AC impedance target is required; decoupling capacitors are added only to suppress resonances and stabilize the plane.
For AC or time-varying loads, the situation is different. The load current fluctuates continuously, so maintaining a low AC impedance becomes essential. Here, decoupling capacitors are used to:
Provide the necessary charge during current transients,
Reduce the AC impedance of the power plane, and
Suppress resonances over the operating frequency range.
When using third-party components, always start by implementing the manufacturer’s recommended decoupling schematic. These recommendations account for the device’s internal design and switching behavior.
However, even after applying the supplier’s guidelines, the designer must still:
Run a PI analysis using the PI Wizard in SIwave, and
Check for unwanted resonances using the Resonant Modes solver.
This ensures that the final PCB meets both stability and power-integrity requirements under real operating conditions.
Applications: CPU, GPU, FPGA, SerDes, DDR
These types of loads draw large amounts of current, but the demand is random and unpredictable. Because of this, it’s nearly impossible to define a constant di/dt or a single transient shape. The resulting frequency content of the load current is broad and stochastic.
In such cases, the designer must focus on keeping the board impedance (Zboard) below a specific target value, Ztarget, defined by:
Ztarget=ΔVallowed/Imax
where
ΔVallowed is the maximum voltage droop allowed by the component specifications, and
Imax is the maximum expected load current.
Open the Capacitor/Inductor Library Browser
→ Tools > Capacitor/Inductor Library Browser
Enter PDN Parameters
→ Specify the VRM (current source) inductance and resistance, as well as the power-plane inductance and resistance.
Add Decoupling Capacitors
Begin with high-frequency capacitors and progressively add larger ones for lower-frequency bands.
The table below provides a practical guideline for typical capacitor values and their corresponding effective frequency bands:
| Capacitor Value | Frequency Band |
|---|---|
| 10 nF | ~70 MHz |
| 0.1 µF | ~20 MHz |
| 1 µF | ~6 MHz |
| 10 µF | ~2 MHz |
| 22 µF | ~1.5 MHz |
| 47 µF | ~1 MHz |
| 100 µF | ~0.7 MHz |
Account for Total Inductance (ESL + Board)
The effective inductance of each capacitor is not just its datasheet ESL — you must also include the loop inductance of the board, which depends on placement.
Approximate board inductance = 0.05 nH per mm of distance from the die.
Example:
If you plan to use 10 capacitors (each with ESL = 0.15 nH) placed 0.5 mm from the die:
Verify Zboard Profile
The resulting Zboard vs. frequency curve should remain below Ztarget across the entire frequency band of interest.
Check for Resonances
After impedance tuning, use Simulation > Resonant Modes in SIwave to confirm that the power plane does not exhibit resonances near any clock frequencies.
If resonances exist, the Resonant Modes solver will suggest optimal capacitor locations and values to suppress them.
Iterate as Needed
Adjust capacitor quantities, values, and placements until both the Z<sub>board</sub> requirement and resonance criteria are satisfied.
Applications: MCU, Logical Gates/Buffers, ADC, DAC, RF driver, pulsed laser, DC/DC converter stage.
In most AC applications, the current demand varies with time. It typically rises from zero to about 90% of its maximum value within a very short period, referred to as RisingTime1 (for example, 0.8 ns). It then increases to 99% of the maximum current over an intermediate period, RisingTime2 (typically around 50× RisingTime1), and finally reaches 100% after a longer period, RisingTime3 (approximately 2000× RisingTime1). After this point, the current remains steady for an extended duration, RisingTime4, which is roughly 300,000× RisingTime1.
The decoupling network generally includes three types of capacitors:
Small / fast / low-ESL capacitors, placed closest to the load — these supply the initial fast current ramp up to RisingTime1.
Medium-value / mid-ESL capacitors, supporting the intermediate current ramp up to RisingTime2.
Bulk / high-ESL capacitors, which provide charge up to RisingTime3, until the VRM responds and supplies current for RisingTime4.
Integrate the current waveform over each time region to determine the total charge (ΔQ) required from each capacitor group.
Estimate the voltage droop for each group by assuming all charge in that interval is drawn from that capacitor set.
→ This defines the minimum capacitance and number of capacitors required per stage.
Add the inductive voltage drop term, VL=L⋅di/dt for each time interval.
L = Lcaps+Lboard
Lcaps=Lsingle/Ncaps
Lboard≈0.05 nH/mm, depending on powerplane shape .
→ This step helps determine both quantity and placement of capacitors.
Sum the capacitive and inductive voltage drops and verify that the total droop is below the maximum allowable voltage drop, ΔVallowed.
After selecting the capacitor network, run a PI analysis using the PI Wizard in SIwave to ensure that the board impedance (Z_board) stays below the target impedance (Z_target) calculated earlier.
Run the Resonant Modes solver to confirm that no power-plane resonances occur near the operating or clock frequencies.
Run the DCIR Wizard to evaluate DC losses and voltage drop in the power plane, using the maximum current (DC to RisingTime4).
→ Use this result to determine the required copper thickness and plane geometry.
Iterate the process as needed until all electrical and thermal constraints are satisfied.
The designer can perform a more detailed evaluation by using AEDT Circuit to accurately analyze the behavior of the decoupling capacitors.
For Case 2, for example, the circuit shown below can be used to study the current and voltage waveforms at any location on the power plane using the Transient Solver in AEDT Circuit. In this setup, the circuit dynamically adjusts the load impedance to match the specified current profile.
It’s also possible to replace the lumped elements with a multiport model generated by the SYZ solver in SIwave.
For instance, by placing three ports corresponding to the three capacitor locations, the model would have five ports in total (two for the source/load and three for the caps).
Alternatively, you can replace all capacitor locations with ports, resulting in a higher-order (>5-port) model.
The capacitors can then be re-inserted in the Circuit schematic for transient analysis.
This type of co-simulation verifies that the PDN behaves as expected.
The resulting plots show the ideal current, the actual current delivered, and the voltage seen by the load — allowing designers to confirm real-world performance against theory.
For Case 1, the same circuit can be reused, but the load impedance should vary in a quasi-random pattern.
A PWL (Piecewise Linear) file can be used to define this time-varying impedance profile for realistic testing.
Inductors are used when a single power rail (for example, 1.2 V) feeds multiple components, and some of those components are noisy while others are noise-sensitive.
Avoid inductors in high-power or high-speed rails, such as CPU, FPGA, SerDes, or DDR supplies.
→ These rails carry large, fast current transients, and any added inductance will cause excessive voltage droop and resonance.
Use inductors or ferrite beads to isolate quiet, low-current rails (typically in the mA range) from noisy digital rails.
→ Examples: analog or RF front ends, PLLs, VCOs, ADCs, DACs, and audio power circuits.
Typical values: 10–100 nH inductors or ferrite beads with 100–600 Ω impedance at 100 MHz.
Use larger inductors at the VRM output (100 nH–10 µH) only as part of an EMI or conducted-emission filter, or when required by the VRM design itself.
Example:
If a 1.2 V CPU rail is very noisy and a small PLL circuit also requires 1.2 V, you can connect both to the same VRM.
However, the PLL should receive its 1.2 V through a small inductor or ferrite bead (≈ 10 nH), creating an isolated “PLL island.” This allows DC power to pass while blocking high-frequency noise from the CPU domain.
Any feedback is welcome.