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SIwave is a power integrity and signals integrity tool. DCIR, one of the power-integrity solvers, is discussed in this article.

DCIR is necessary to study the voltage and current distribution of the powerplane distribution network PDN. The solver calculates the voltage drop in any power plane, voltage rise in the ground plane, the current distribution, the current in each via, detects overloading in any via, detects any massive current accumulation, identifies locations of potential ESD issues, and many other defects.


Figure 1: DC IR solver 4th icon from the left

SIwave should not be used to build PCBs. While this is possible, it is not the best way to utilize SIwave. SIwave can import the following type of CAD files:


Figure 2: Import dialog box in SIwave

SIwave extracts much information from the CAD file, for example, the stackup, the materials, the components, and the nets. So what is missing? Is assigning ports. That is all. Before using SIwave, it is highly recommended that the user reads the electrical schematic very well; it will save lots of time.

Siwave, like any other PI tool, understands the language of nets. When a board is imported, SIwave immediately starts looking for single nets. And the single net is an electrically connected structure without the use of any external component. A single net could occupy many layers but cannot be electrically disconnected. To analyze a power plane, one needs to identify its nets. It could have just one net, and it could have many nets. And if there are many nets, they should be connected using resistors or inductors. That is what is called a passive link. If integrated/discrete components exist along the path, then SIwave will treat each side of the integrated/discrete component as an independent link.

Green: single nets

Red: passive components (resistors/inductors)

Black: Discrete components


Figure 3: Single nets, Passive links, and Powerplane full link

Any process in SIwave: DC, PI, SI, or radiation starts by selecting a solver. Once a solver has been selected, SIwave generates a dialog box that looks like a form. The user needs to check the form and fill up the missing information. For example, the figure below shows the dialog box of the DCIR solver. The user selects one passive link (its nets) from the left box, and SIwave populates the right box with all the connections. The user specifies the location of the ports. In any powerplane, one usually knows the voltage at one location, which is the output of the VRM, and knows only the current that each die on the powerplane is withdrawing. So assign a voltage at the output of the VRM and a current at the CPU. Current source simply means that the current amplitude is known; it does not mean that it is a current source. Repeat the process for each passive link. Then the solver is launched.

In the setup, assign a name. Also, in the table below, make sure to assign anything that is a voltage source to be negative. Negative confirms that the net in the negative column is indeed the reference plane of the voltage source. For the current sources, keep it Neither. So the DCIR will decide the direction of the current. Other solver options to control the accuracy of the solver.


Figure 4: Enter ports dialog box

  1. Debug the solver:
Refinement statistics

Examine the refinement process. This option tells the user if the solution went smoothly. One needs to see the power error decreasing in a monotonic way. The vibration in the error indicates a major issue with the 3D model.


Figure 5: Refinement statistics


The profile is another important means to examine the solution. It gives an idea of the solver timing and the mesh used in each net. This information is used to compare different models. The user can also use this information to plan long runs.


Figure 6: Profile information


SIwave allows the user to review the solver setup used anytime in the future. Then the user can tell what setup was used to produce the results.

  1. Examining the solution:
Voltage drops in the Vcc

DCIR calculates the voltage drop in the powerplanes. Right-click on the solution and activate plots Current/Voltage. Then by displaying the voltage on each layer, one can track the voltage drop in any powerplane from the source to the load. One can hover the mouse over the nets to see the values at different locations. What the user is looking for is a smooth transition of the voltage. One expects to see very small changes in large powerplane. Any small delta means lots of power dissipation. If that is not the case, then one needs to redesign the power network.

Picture25Figure 7: Voltage distribution

Voltage rise in the ground

In addition to checking the voltage drop in the Vcc nets, users also need to check the voltage of the ground at the load. Sometimes the problem is on the ground side, causing the ground voltage to be higher than zero volt. In the model shown below, the ground voltage is 0.3mV at load.


Figure 8: Voltage rise on the ground

Current distribution and direction

The current distribution is one of the results for the DCIR solver. It provides information about any bottleneck issue in the power plane network or in the ground plane. SIwave provides two pieces of information in the plots: the current's magnitude and direction. Any concentration of current, in red, must be examined by the user. If it turns out that the section is narrow, then one needs to find a way to widen it. Also, watch for any sharp corners. If one notices that the current flows in an irregular way, around sharp corners, then there is a potential for an ESD issue with time. Always, even with DC applications, avoid having sharp corners.


Figure 9: Current Distribution

Current density in Vias

The current distribution in the vias is the most important results of the DCIR solution. In SIwave, select the option Display Element Data. From the table, choose Vias. SIwave will display all the vias and how much current is running through. It also highlights if any via is carrying too much current. The limit is specified in a file called "dc_coeff.txt." The default number, determines if the via will pass or fail the test. The user can change the number, but the default numbers are standards. If any via carry too much current, the probability of a PCB failure becomes very high. Designer then needs to increase the number of vias, or use wider vias.


Figure 10: Vias violation checking list


Figure 11: dc_coeff.txt

Current density in the metals

SIwave also allows the user to verify if the metal is carrying too much current in any location. In the same panel above, choose Metallization. SIwave can identify sections with a voltage higher than a specific value, a current density above a specific value, or a power density above a specific limit. Such capability, if used properly and the issues identified and fixed, can save the user lots of future issues.


Figure 12: RLGC equivalent circuit

Voltage probes

Users can also add voltage probes when assigning ports, voltage sources, and current sources. These voltage probes can be placed on any connection. By referring to the above dialog box and selecting the Voltage probe panel, one can see the voltages at the locations where there are voltage probes.

Power distribution

Power distribution in all the layers can be extracted from the current distribution. This information is important if the user wants to do a thermal analysis. In this case, the Icepack program inside SIwave will convert the power distribution into temperature distribution. The power distribution is also used to calculate the PCB's median time to failure MTTF. The MTTF solver is also available within SIwave. So power distribution is necessary data for more advanced calculations.


Figure 13: Power distribution

Loop resistance

Based on the I-V response of any powerplane passive link, SIwave can derive the loop resistance of the link. That is the total resistance of both the Vcc and the ground links. This number is the number that the user needs to consider in doing investigations, and not just the resistance of the positive side.


Figure 14: Loop resistance output

Path resistance and RL Table

The path resistance table provides more detailed information about the resistance of each link, the positive on Vcc, and the negative on the ground plane. The summation of both paths is the loop resistance. Both information can be found using the path resistance or the RL table option.


Figure 15: Path resistance output


Figure 16: RL Table output

  1. Export Features:
Power Tree

SIwave can produce a power tree flowchart. It has the connections between the different parts in the link, as well as the direction of the current, the amplitude of the current in each branch, and the voltage drop. When one has tens of powerplanes with lots of dies on each link, it is very important for the user to produce this flowchart to confirm that the connections inside the model are correct. The flowchart is the best way to confirm that. It also summarizes all the results in a graphical way, making it easy to understand the current flow inside the PCB.


Figure 17: PDN FlowChart

Spice Subcircuit

SIwave can generate a DC spice model of the powerplane. SIwave supports many forms, like HSPICE, Maxwell Spice, Cadense PSPICE, Cadence Spectre, and SIMetrix Simplis.


Figure 18: Spice model



Checking the solution, displaying data in many forms, and exporting data in many formats: these are things that the user of SIwave can do using SIwave DCIR solver.


SIwave, DCIR
Hatem Akel
Post by Hatem Akel
May 31, 2023